RISC-V cores are starting to appear in heterogeneous SoCs and packages, moving from one-off standalone designs to mainstream applications where they are used for everything from gas pedals and additional processing cores to secure applications.

These changes are subtle but significant. They point to the growing acceptance that chips or small chips based on open-source instruction set architectures can be combined with silicon-proven cores from the likes of Arm, Synopsys (ARC) and Cadence (Tensilica Xtensa) to create relatively inexpensive and flexible customization options. While RISC-V has yet to make inroads into standalone applications, companies such as Ventana Micro Systems are testing the waters for RISC-V-based high-performance computing chips for data centers.

RISC-V is unlikely to replace existing chip architectures any time soon, but it is sure to attract significant attention from the hardware design community as it moves from monolithic, single-vendor SoCs to heterogeneous, multi-chip advanced packaging. According to a recent Semico Research report, RISC-V IP is expected to grow at a compound annual growth rate of 34.9 percent through 2027, compared to 9 percent for semiconductor IP.

According to RISC-V International, there are also more than 3,180 RISC-V members in 70 countries, including 94 chip companies and four system companies. With increasing pressure from government agencies to cut development costs and time, this market is clearly worth watching.

"It looks a lot like the ASIC model again," said Sailesh Chittipeddi, executive vice president of Renesas Electronics. "But it's no longer about the CPU performing X, Y and Z functions for each workload without the overhead associated with it. Instead, all of these companies are becoming more verticalized to drive the solutions they need, whether it's artificial intelligence or something else at the system level. That's why we're seeing more and more CAD companies getting more and more into system-level support and system-level design. Now you can go deeper into each of those areas. More broadly, we're seeing a systemic shift in the industry and a shift to providing solutions."

RISC-V is becoming an integral part of these heterogeneous solutions, and it is gaining attention for two main reasons. First, the open source ISA allows it to be customized relatively simply, although for critical applications it still requires verification and testing using commercial EDA tools. Second, no royalties are paid once the design is complete, so for design teams with experienced processor engineers, RISC-V cores can be used to create customer or application-specific designs without paying royalties.

In short, while there is only one standard ISA, there are many possible implementations. "It's similar to Ethernet," says Calista Redmond, CEO of the RISC-V Foundation. "There is one standard, but not just one vendor. The difference is that RISC-V takes a modular approach. There is a base set of 47 instructions, and you can add any extensions needed for different workloads. There is also an extensive roadmap with different parts from 81 different working groups that will be approved and validated to meet security and safety standards.

The focus, however, is on experienced engineering skills. For example, unlike the Arm kernel, integrating RISC-V is not straightforward. Any RISC-V implementation needs to be fully characterized in the context of the use case, the final application, other components within physical proximity, and how those components affect other components. Connectivity and the potential impact of that connectivity on other components needs to be fully understood and fully characterized under all known or expected conditions.

"At any given moment, you can address it as best you can for the chip you're developing right now," said Synopsys researcher Rob Aitken. "Next time, you'll have a new CPU and newer bandwidth in the outside world, and probably in a situation where everyone is starting to adopt UCIe. But you still have to go back to your overall chip or system architecture and determine what it is that you want to accomplish. You have some kind of computing system, somewhere with memory, and different kinds of GPUs or gas pedals. Then there's the question of how to get all these colored boxes in PowerPoint to communicate with each other, because at some point, when you actually connect them together, you may find this huge bottleneck that you have to figure out how to solve."

Toward heterogeneity

This is the challenge of heterogeneous design, because not all modules in an SoC or chips/small chips in an advanced package are developed by the same engineering team. In many cases, they are not even developed in the same country. From an integration perspective, the more components there are, the more complex it all becomes.

"One of the things that has surprised people about the move to RISC-V is the freedom to innovate," says Simon Davidmann, president and CEO of Imperas Software. "We have customers who spend a lot of time on the network to save chips. It's entirely about how the chips communicate with each other, what the network looks like, what the communication looks like. They have to verify and validate all of that, not only from a functional standpoint, but also from a performance standpoint. We're all on the same core, but what's different is the interconnect and how things communicate. risc-V enables you to buy a core, configure it, drop a thousand or a hundred cores, add a vector engine, and then make yourself stand out with the network you have and the software on top."

Others agree. "In the MCU space, all these companies were running proprietary courses where you had hardware and software that you could deliver to your customers -- complete solutions," says Renesas' Chittipeddi. "Then came Arm, which created an environment where we had flexible software packages and Arm cores. Now there's RISC-V. We caught the wave a little earlier than others, so while people were doing test chips, we came out with products optimized for motor control applications. This year we optimized RISC-V for voice applications. we can extend the concept to other areas as well. the shift that's happening on the MCU side and the MPU side is significant, and RISC-V is helping our automotive business to follow suit quickly."

But while the benefits of RISC-V are becoming more apparent, so are the potential problems. Davidmann says that quality and verification are huge challenges for the RISC-V community, which often cannot afford the same number of verification cycles as some of the larger processor companies. He said, "We have to work together and collaborate to build the application ecosystem because the quality of the cores will be a big challenge going forward."

Security

Security is one of the growth areas in the ecosystem, both for development tools and cryptographic cores, as well as for the security of the chips themselves.

According to Rupert Baines, chief marketing officer at Codasip, chips that include RISC-V have a clear advantage in terms of security, in part because it is based on open-source code. "There's more emphasis on 'sunlight is the best disinfectant,' so there's more emphasis on watching, examining and observing things," he said. Ultimately, security depends on how the architecture is implemented. "Some systems will be very bad and some systems will be very, very good."

Codasip recently acquired Cerberus Security Labs, and Baines said Codasip is integrating Cerberus' IP into Codasip products so customers can quickly create secure RISC-V processor designs.

RISC-V can also be used as a customizable core for security solutions. For example, Rambus developed a programmable root-of-trust tamper-proof kernel for government and military applications several years ago that includes AES, RSA, and ECC encryption gas pedal kernels as well as a true random number generator.

Riscure has also developed specialized simulators to emulate the security properties of using RISC-V.

Maarten Bron, Managing Director of Riscure, said, "It demonstrates the efficacy of hardware versus software countermeasures in the chip and how hardware countermeasures can actually increase the effectiveness of software countermeasures by a factor of 10."

Next steps

What's clear about RISC-V is that the entire ecosystem is evolving rapidly, and EDA vendors are competing to position their tools around RISC-V.

Case in point: Siemens EDA has introduced debugging tools based on the RISC-V working group standard, which is currently in its second revision. "A lot of design is more than just RISC-V," says Peter Shields, Tessent product manager at Siemens EDA. "Understanding the behavior of programs in complex systems is a huge challenge. It is often very impractical to stop the kernel to debug the software. This is particularly true in the context of real-time systems, where the nature of the system does not wait when the core is stopped. Therefore, what is needed is a non-invasive way to observe program behavior at full speed. This allows you to see exactly how the software is executing in the system and how it is responding to real-time events. Processor tracing gives you the ability to absolutely capture sequences of executed instructions without stopping the kernel."

Other challenges have less to do with RISC-V than with the reality of using smaller nodes. "All of these scaling issues and challenges arise when we move to smaller nodes," says Davidman. "It's the physical mechanism of building these things and putting them on the device. We're just starting to work with some other companies at the SoC level, and if we get to the system level, it's going to be a long, slow process."

The move into data centers and automotive applications will put more pressure on improving the reliability of RISC-V designs. Researchers at the Universities of Bologna and Modena in Italy and ETH Zurich have developed an open-source RISC-V-based SoC capable of running Linux with ultra-low power consumption, and researchers at the Barcelona Supercomputing Center in Spain have recently introduced a vector processing acceleration engine with integrated RISC-V vector extensions.

How these projects will perform relative to existing processors remains to be seen, but this move illustrates the growth and ambition of the RISC-V ecosystem.

Conclusion

While RISC-V is unlikely to replace existing chip architectures anytime soon, the growth of RISC-V cores in heterogeneous SoCs and packages indicates that this open source instruction set architecture is becoming more mainstream. the advantages of RISC-V include the ability to customize and re-customize, and the fact that no royalties are paid once the design is complete. In addition, it can provide security advantages due to the large number of companies and engineers collaborating on the open source code.

At the same time, RISC-V integration is not straightforward and requires additional applications to manage core quality and verification. As this rapidly evolving ecosystem matures, it is sure to show new advantages and challenges.